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delaying the monotone sign utilizing Every single on the plurality of resettable delay line segments to produce a respective plurality of delayed monotone signals Every having either a one or a zero logic benefit; and
The method from the creation can be carried out determined by combinatorial logic working with static CMOS, which is fairly cost-effective based mostly the processor's existing circuit integration. Detection payment for process, voltage, and temperature variants of your hold off traces, can be attained by adapting the number of delay lines and multi-frequency program help.
2. The method for detecting clock tampering as outlined in claim one, even further comprising: resetting the resettable hold off line segments in the course of a reset period of time, whereby the reset period of time is prior to the clock Examine time frame.
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The next circuit delivers a 2nd monotone sign during a second clock evaluate time period linked to the clock. The second clock evaluate time frame covers a different time than the main clock Assess time period. The 2nd plurality of resettable delay line segments Every delay the main monotone sign to deliver a respective second plurality of delayed monotone signals. Resettable delay line segments amongst a resettable delay line segment connected to a minimum delay time and a resettable hold off line phase related to a greatest delay time are Every single related to discretely growing hold off read more moments. The evaluate circuit is brought on through the clock and employs the 1st plurality of delayed monotone signals or the 2nd plurality of delayed monotone signals to detect a clock fault.
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4. The method for detecting clock tampering as outlined in claim 1, wherein the Assess circuit decides whether the amount of kinds while in the plurality of delayed monotone indicators differs from a water degree number by much more than a predetermined threshold.
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The hold off amongst the reset operators of one other sensing circuits might be considerably less stringent and should be based on the best acceptable working frequency.
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40. The apparatus for detecting voltage tampering as described in claim 37, whereby the Assess circuit decides whether or not the volume of ones in the plurality of delayed monotone indicators differs from the h2o amount variety by a lot more than a predetermined threshold to detect the voltage fault.
In other more thorough facets of the creation, Each and every of your plurality of delayed monotone indicators could be both a one particular or simply a zero. The Examine circuit may well establish whether the quantity of types while in the plurality of delayed monotone alerts differs from a drinking water amount range by a lot more than a predetermined threshold.